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| FSA2258 -- Low-Voltage Dual-SPDT (0.8) Analog Switch with 16kV ESD July 2009 FSA2258 Low-Voltage, Dual-SPDT (0.8) Analog Switch with 16kV ESD Features 0.8 Typical On Resistance (RON) for +3.0V Supply 0.40 Maximum RON Flatness for +3.0V Supply -3db Bandwidth: > 50MHz Low ICCT Current Over an Expanded Control Input Range Packaged in 10-Lead MicroPakTM (1.6 x 2.1mm) Power-Off Protection on Common Ports Broad VCC Operating Range: 1.65V to 4.30V HBM JEDEC: JESD22-A114 - I/O to GND: 9kV - Power to GND: 16kV Description The FSA2258 is a high-performance, dual, Single Pole Double Throw (SPDT) analog switch that features low RON of 0.8 (typical) at 3.0V VCC. The FSA2258 operates over a wide VCC range of 1.65V to 4.3V and is designed for break-before-make operation. The select input is TTL-level compatible. The FSA2258 features very low quiescent current even when the control voltage is lower than the VCC supply. This feature suits mobile handset applications by allowing direct interface with baseband processor general-purpose I/Os with minimal battery consumption. IMPORTANT NOTE: For additional information, analogswitch@fairchildsemi.com. please contact Applications Cell Phone, PDA, Digital Camera, and Notebook LCD Monitor, TV, and Set-Top Box Ordering Information Part Number Top Mark FSA2258L10X JS Operating Temperature Range -40 to +85C Eco Status Green Package 10-Lead MicroPakTM 1.6 x 2.1mm, JEDEC MO-255B For Fairchild's definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Analog Symbol 1B0 1B1 2B0 2B1 2A S2 1A S1 Figure 1. FSA2258 (c) 2008 Fairchild Semiconductor Corporation FSA2258 * Rev. 1.0.2 www.fairchildsemi.com FSA2258 -- Low-Voltage, Dual-SPDT (0.8) Analog Switch with 16kV ESD Pin Configuration Vcc 10 1B0 1B1 2B0 2B1 1 2 3 4 5 GND Figure 2. 10-Lead MicroPakTM (Top-Through View) 9 8 7 6 1A S1 S2 2A Pin Descriptions Pin # 1 2 3 4 5 6 7 8 9 10 Name 1B0 1B1 2B0 2B1 GND 2A S2 S1 1A VCC Data Ports Data Ports Data Ports Data Ports Ground Data Ports Switch Select Pins Switch Select Pins Data Ports Supply Voltage Description Truth Table Control Input, Sn LOW Logic Level HIGH Logic Level Function nB0 connected to nA nB1 connected to nA (c) 2008 Fairchild Semiconductor Corporation FSA2258 * Rev. 1.0.2 www.fairchildsemi.com 2 FSA2258 -- Low-Voltage, Dual-SPDT (0.8) Analog Switch with 16kV ESD Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VCC VSW VIN IIK ISW ISWPEAK TSTG TJ TL Supply Voltage Switch I/O Voltage (1) (1) Min. -0.5 1B0, 1B1, 2B0, 2B1, 1A, 2A Pins S1, S2 -0.5 -0.5 Max. 5.5 VCC + 0.3 5.5 -50 350 500 Units V V V mA mA mA C C C Control Input Voltage Input Clamp Diode Current Switch I/O Current (Continuous) Peak Switch Current (Pulsed at 1ms Duration, <10% Duty Cycle) Storage Temperature Range Maximum Junction Temperature Lead Temperature (Soldering, 10 seconds) I/O to GND Human Body Model, JEDEC: JESD22-A114 Power to GND All Other Pins Charged Device Model, JEDEC: JESD22-C101 -65 +150 +150 +260 9 16 9 2.0 ESD kV Note: 1. Input and output negative ratings may be exceeded if input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VIN VSW TA Supply Voltage Control Input Voltage Switch I/O Voltage Operating Temperature Parameter Min. 1.65 0 0 -40 Max. 4.30 VCC 4.3 +85 Units V V V C (c) 2008 Fairchild Semiconductor Corporation FSA2258 * Rev. 1.0.2 www.fairchildsemi.com 3 FSA2258 -- Low-Voltage, Dual-SPDT (0.8) Analog Switch with 16kV ESD DC Electrical Characteristics All typical values are at 25C unless otherwise specified. Symbol Parameter Conditions VCC (V) Min. VIH Control Input Voltage HIGH 3.60 to 4.30 2.70 to 3.60 2.30 to 2.70 1.65 to 1.95 3.60 to 4.30 2.70 to 3.60 2.30 to 2.70 1.65 to 1.95 VIN=0 to VCC nA=0.3V, VCC-0.3V nB0 or nB1=VCC-0.3V, 0.3V, or Floating Figure 4 nA=0.3V, VCC-0.3V nB0 or nB1=VCC-0.3V, 0.3V, or Floating Figure 5 Common Port (1A, 2A), VIN=0V to 4.3V, VCC=0V nB0, nB1=Floating ION=100mA, nB0 or nB1=0.7V, 3.6V Figure 3 ION=100mA, nB0 or nB1=0.7V, 2.3V Figure 3 RON Switch On Resistance(2 ,5) ION=100mA, nB0 or nB1=0V, 0.7V, 1.6V, 2.3V Figure 3 ION=100mA, nB0 or nB1=0V, 0.7V, 1.65V Figure 3 On Resistance Matching Between Channels(3, 5) ION=100mA, nB0 or nB1=0.7V 1.65 to 4.30 TA=+25C TA=-40 to +85C Unit Typ. Max. Min. 1.7 1.5 1.4 0.9 Max. V 0.7 0.5 0.4 0.4 VIL Control Input Voltage LOW V IIN INO(0FF), INC(OFF) Control Input Leakage (S1,S2) Off Leakage Current of Port nB0 and nB1 -0.5 0.5 A 1.95 to 4.30 -10 10 -50 50 nA IA(ON) On Leakage Current of Port nA Power-Off Leakage Current (Common Port Only 1A, 2A) 1.95 to 4.30 -20 20 -100 100 nA IOFF 0 1 A 4.30 0.5 1.0 3.00 0.8 1.2 2.30 1.1 1.65 4.30 3.00 2.30 1.65 4.30 3.00 2.30 1.65 4.30 4.30 -100 1.5 0.08 0.20 0.40 0.50 0.25 0.25 RON RFLAT(ON) On Resistance Flatness (4 ,5) IOUT=100mA, nB0 or nB1=0V to VCC VIN=0 or VCC, IOUT=0 Input at 2.6V Input at 1.8V 0.4 0.4 0.9 1.2 100 3 7 -500 500 7 15 nA A ICC ICCT Quiescent Supply Current Increase in ICC per Input Notes: 2. On resistance is determined by the voltage drop between A and B pins at the indicated current through the switch. 3. RON=RON max - RON min measured at identical VCC, temperature, and voltage. 4. Flatness is defined as the difference between the maximum and minimum value of on resistance (RON) over the specified range of conditions. 5. Guaranteed by characterization, not production tested for VCC=1.65 - 3.0V. (c) 2008 Fairchild Semiconductor Corporation FSA2258 * Rev. 1.0.2 www.fairchildsemi.com 4 FSA2258 -- Low-Voltage, Dual-SPDT (0.8) Analog Switch with 16kV ESD AC Electrical Characteristics All typical value are for VCC=3.3V at 25C unless otherwise specified. Symbol Parameter Conditions VCC (V) 3.60 to 4.30 2.70 to 3.60 2.30 to 2.70 1.65 to 1.95 3.60 to 4.30 2.70 to 3.60 2.30 to 2.70 1.65 to 1.95 3.60 to 4.30 2.70 to 3.60 2.30 to 2.70 1.65 to 1.95 1.65 to 4.30 TA=+25C TA=-40 to +85C Max. 60 65 70 5 5 5 2 2 2 2 35 40 45 Unit Figure Min. Typ. Max. Min. Turn-On Time nB0 or nB1=1.5V, RL=50, CL=35pF nB0 or nB1=1.5V, RL=50, CL=35pF 55 60 65 70 30 35 40 40 15 15 15 16 25 -70 -70 >50 tON ns Figure 6 Figure 7 ns tOFF Turn-Off Time tBBM nB0 or BreaknB1=1.5V, Before-Make RL=50, (6) Time CL=35pF Charge Injection(6) Off Isolation(6) Crosstalk(6) -3db Bandwidth(6) Total Harmonic Distortion + Noise(6) CL=1.0nF, VS=0V, RS=0 ns Figure 8 Q OIRR Xtalk BW pC dB dB MHz Figure 12 Figure 10 Figure 11 Figure 9 f=100kHz, 1.65 to 4.30 RL=50, CL=0pF f=100kHz, 1.65 to 4.30 RL=50, CL=0pF RL=50, CL=0pF 1.65 to 4.30 f=20Hz to 20kHz, 1.65 to 4.30 RL=32, VIN=2VPP THD+N .06 % Figure 15 Note: 6. Guaranteed by characterization, not production tested Capacitance All capacitance specifications are guaranteed by characterization and are not production tested. Symbol CIN COFF CON Parameter Control Pin Input Capacitance B Port Off Capacitance A Port On Capacitance Conditions VCC (V) f=1MHz f=1MHz f=1MHz 0 3.3 3.3 TA=+25C Min. Typ. 1.5 30 120 Unit pF pF pF Figure Figure 13 Figure 13 Figure 14 Max. (c) 2008 Fairchild Semiconductor Corporation FSA2258 * Rev. 1.0.2 www.fairchildsemi.com 5 FSA2258 -- Low-Voltage, Dual-SPDT (0.8) Analog Switch with 16kV ESD Test Diagrams VON NC nBn V IN GND I A(OFF) A nA V IN Select V Sel = I ON GND Select VSel = GND 0 orVcc R ON = VON / ION Figure 3. 0 or Vcc **Each switch port is tested separately. On Resistance Figure 4. Off Leakage (Ports Tested Separately) NC I A(ON) nBn V IN nA A V IN Select VSel = GND GND RS CL GND RL V OUT 0 or Vcc V Sel GND Figure 5. On Leakage Figure 6. Test Circuit Load tRISE = 2.5ns VCC Input - VSel GND VOH Output - VOUT VOL 10% 90% VCC /2 90% VCC /2 tFALL = 2.5ns 10% 90% 90% tON tOFF Figure 7. Turn-On / Turn-Off Waveforms (c) 2008 Fairchild Semiconductor Corporation FSA2258 * Rev. 1.0.2 www.fairchildsemi.com 6 FSA2258 -- Low-Voltage, Dual-SPDT (0.8) Analog Switch with 16kV ESD Test Diagrams (Continued) tRISE = 2.5ns nB n V IN GN D nA V cc V IN GN D CL G ND VOUT R L Input - VSel 0V V OUT 0.9*V out 10% 90% V cc /2 RS 0.9*V out V S el GN D RL and CL are functions of the application environment (50, 75, or 100 ). CL includes test fixture and stray capacitance. Figure 8. Break-Before-Make Interval Timing tBBM Network Analyzer RS GND V IN V S GND VSel GND GND VOUT RT GND RL and CL are functions of the application environment (50, 75, or 100 ). L CL includes test fixture and stray capacitance. Figure 9. Bandwidth Network Analyzer RS GND RT VSel GND GND VS GND VOUT GND RT GND RS and RT are functions of the application environment (50, 75, or 100 ). Off-Isolation = 20 Log (VOUT / VIN ) - Figure 10. Channel Off Isolation (c) 2008 Fairchild Semiconductor Corporation FSA2258 * Rev. 1.0.2 www.fairchildsemi.com 7 FSA2258 -- Low-Voltage, Dual-SPDT (0.8) Analog Switch with 16kV ESD Test Diagrams (Continued) Network Analyzer RS VIN VS GND GND VSel GND GND RT GND RT GND V OUT RS and RT are functions of the application CROSSTALK = 20 Log (VOUT / VIN ) environment (50, 75, or 100 ). Figure 11. Adjacent Channel Crosstalk Generator B VS RS GND nSn VSEL GND VIN mA CL GND VOUT VCC Input - VSEL 0V VOUT VOUT Off On Off CL includes test fixture and stray capacitance Q = VOUT / CL Figure 12. Charge Injection Test nBn Capacitance Meter f = 1MHz nBn nSn VSel = Capacitance Meter nBn nSn V Sel = nBn 0 or Vcc f = 1MHz 0 orVcc Figure 13. Channel Off Capacitance Figure 14. Channel On Capacitance Audio Analyzer RS GND V IN VS GND V CNTRL GND GND V OUT RT GND VSel = 0 or Vcc RS and RT are functions of the application environment (see AC Tables for specific values). Figure 15. Total Harmonic Distortion (c) 2008 Fairchild Semiconductor Corporation FSA2258 * Rev. 1.0.2 www.fairchildsemi.com 8 FSA2258 -- Low-Voltage, Dual-SPDT (0.8) Analog Switch with 16kV ESD Physical Dimensions 0.10 C 2X 2.10 A B (0.11) 0.56 1.62 KEEPOUT ZONE, NO TRACES OR VIAS ALLOWED 1.60 PIN1 IDENT IS 2X LONGER THAN OTHER LINES 0.10 C 1.12 TOP VIEW 2X 0.50 (0.35) 10X (0.25) 10X RECOMMENDED LAND PATTERN 0.55 MAX 0.05 C 0.05 C C 0.05 0.00 (0.20) 0.35 0.25 (0.15) 0.35 0.25 SIDE VIEW D 0.65 0.55 1 4 DETAIL A 0.35 0.25 (0.36) 0.56 5 DETAIL A 2X SCALE NOTES: A. PACKAGE CONFORMS TO JEDEC REGISTRATION MO-255, VARIATION UABD . B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. PRESENCE OF CENTER PAD IS PACKAGE SUPPLIER DEPENDENT. IF PRESENT IT IS NOT INTENDED TO BE SOLDERED AND HAS A BLACK OXIDE FINISH. E. DRAWING FILENAME: MKT-MAC10Arev5. 10 (0.29) 0.50 9 6 0.25 9X 0.15 1.62 0.35 9X 0.25 0.10 0.05 CAB C ALL FEATURES BOTTOM VIEW Figure 16. 10-Lead MicroPakTM Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2008 Fairchild Semiconductor Corporation FSA2258 * Rev. 1.0.2 www.fairchildsemi.com 9 FSA2258 -- Low-Voltage, Dual-SPDT (0.8) Analog Switch with 16kV ESD (c) 2008 Fairchild Semiconductor Corporation FSA2258 * Rev. 1.0.2 www.fairchildsemi.com 10 |
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